Raman integral chips. Decifrangers TTL series Method for increasing the number of exits of the decoder
We reviewed a single-stage decoder (linear) - it is the most high-speed, but its implementation with a significant bit of the input word is difficult because it requires the use of logical elements with large number Inputs, which is accompanied by a large load on the sources of input signals. Usually, single-stage decoders are performed to a small number of inputs, determined by the capabilities of the elements of the used microcircuit series. Therefore, often the number of conclusions of the decoder is not enough to select the necessary number of microprocessor equipment devices. Using two decoders with resolving input E, it is possible to implement a decoder with the number of outputs n \u003d 2 n + 1 (Fig. 2.11.3).
Fig. 2.11.3. 3x8 decoder based on two decoders 2x4
In fig. 2.11.3 shows the scheme of the combined decoder 3x8, implemented on two complete decoders 2x4. Thus, it is possible from 2 decoders 3x8 to create an decoder 4x16, etc. Allive input E is used as the address discharge. When E \u003d 0, the upper decoder works, at e \u003d 1 operates the lower decoder, while all the outputs of the upper decoder are equal to 0.
Another cascade (pyramidal) method is widely used. A method for constructing decoders with a large number of outputs on seifratum chips with a smaller number of outputs (Fig.2.11.4).
To resolve the operation of one of the decoders 3x8 (DC2, DC3, DC4, DC5), the allowing or prohibiting signal from the DC1 decoder (first stage), which is controlled by address discharges A3, A4, is supplied to the input E of each decoder.
Fig. 2.11.4. Cascading (pyramidal) scheme for decifra
Address discharges A0, A1, A2 are submitted in parallel to the 2nd cascade decoders. The total number of targeted discharges increased by 2 discharge.
Encodes. Encodes are devices designed to convert unitary code into binary. A multi-digit binary code appears at the output of the encoder, corresponding to the decimal entry number to which the active logical level is filed. Binary encoders perform operation, reverse operation of decodifrators.
The encoder is sometimes called the "encoder" (from the English. Coder) and use, for example, for translation decimal numbersScored on the keyboard of the control panel in binary numbers. If the number of inputs is so large that all possible combinations of output signals are used in the encoder, then such an encoder is called complete. The number of inputs and outputs in a full encoder is associated with the ratio n \u003d 2 n, where n is the number of inputs, n is the number of outputs. So, to convert the button of the push-button console in a four-digit binary number, it is sufficient to use only 10 inputs, while the total number of possible inputs will be 16 (n \u003d 2 4 \u003d 16), so the 10x4 encoder will be incomplete.
Consider an example of constructing a encoder to convert a ten-bit unit code (decimal numbers from 0 to 9) to binary code. It assumes that a signal corresponding to a logical unit, only one input is supplied at each time.
The truth table for the encoder is shown in Table 2.11.3.
Using this table, write logical expressions for output variables, including in the logical sum, the input variables that correspond to the unit of the corresponding output variable.
Truth Table for Decifranger
Table 2.11.3.
| Inputs | Outputs | |||||||||||||
| № | X0. | X1. | X2 | X3. | X4. | X5 | X6. | X7. | X8. | X9. | A3. | A2. | A1 | A0. |
We write logical equations for output variables A0, A1, A2, A3:
A0 \u003d x1 v x3 v x5 v x7 v x9
A1 \u003d x2 v x3 v x6 v x7
A2 \u003d x4 v x5 v x6 v x7
For such an encoder it is easy to build a scheme on the logical elements "or" (Fig. 2.11.5).
Fig. 2.11.5. Incomplete encoder 10x4 scheme
Guidelines for work:
Write down in the report, as usual, the name of the work, the goal of the work. Bring the definition definition. Make a truth table for an decoder having 3 address entries. Record the equations for each of the 8th decodes of the decoder. Build a scheme. Collect a scheme that implements the functions of the decoder in Multisim. Explore her work.
Explore the operation of the 2x4 decoder chip. Collect the decoder scheme shown in Fig. 2.11.4 Using only 2x4 decoders.
Get temporary charts of the scheme. To show all the input and output signals of the decoder, use 2 analyzers.
Draw a scheme and explain in the report of its work. Give temporary charts. Temporary charts must be brought on one page, you can not continue the time-related schedules on another page. All links between signals must be visual.
Make a truth table for a complete encoder 8x3. Write down the logical functions of the output variables. Build and explore the encoder scheme. In the report, bring the table of truth, the equation constructed by the equations scheme, temporary charts.
Write down the conclusions appropriate to each item.
Questions to prepare for the report:
1. Give the definition definition.
2. Give the definition of the encoder.
3. What do you understand under the unitary code?
4. What is the difference between a complete decoder from incomplete?
5. What is the difference between a full encoder from incomplete?
6. What is the difference between the linear decoder from the pyramidal?
7. More speed in linear decoder or pyramidal?
8. More hardware costs required to implement a linear decoder or pyramidal?
9. What is used in computing technology Decifranis and encoders?
12. Laboratory work number 12
Research of multiplexers and demultiplexers
Purpose of work:Examine the principles of synthesis and operation of multiplexers and demultiplexers.
The task:Synthesize the multiplexer scheme, explore the scheme operation. Explore the multiplexer chip, build and explore the work of the pyramidal scheme. Synthesis of the demultiplexer scheme, investigate the operation of the scheme. Explore the collaboration of the multiplexer and demultiplexer.
Multiplexer called a combination logical device intended for managed transmission Data from multiple sources of information in one output channel. Multiplexer inputs are divided into information D. 0 , D. 1, ...... and managers (address) BUT 0 , BUT 1 , …, BUT N-1.
The code submitted to the address inputs determines which of the information inputs to this moment Transmitted to the output of the circuit. Insofar as n.-Reveloped binary code can take 2 n values, if the number of targeted multiplexer inputs is equal n.The number of its information inputs should be 2 n.
We construct a truth table that displays a multiplexer with two targeted inputs based on the definition. Denote in Table A0 and A1 - address inputs. D0, d1, d2, d3 - inputs of 4 data streams, when setting the address, the corresponding data will be transmitted to the only yield of the multiplexer Y (Table 2.12. 1).
The table has the following form:
Table 2.12. one
| Address | Data | Output | ||||
| A1. | A0. | D0 | D1 | D2. | D3. | Y. |
| D0 | D1 | D2. | D3. | D0 | ||
| D0 | D1 | D2. | D3. | D1 | ||
| D0 | D1 | D2. | D3. | D2. | ||
| D0 | D1 | D2. | D3. | D3. |
We write the equation for the Y function:
Y \u003d A1 * A0 * D0 V A1 * A0 D1 V A1 A0 * D2 V A1 A0 D3.
The scheme implementing the function Y can be built on 2 inverters, 4-three-line elements "and" and four-hundred-to-element "or" elements (Fig. 12.2.1).
Fig. 12.2.1. Multiplexer 4-1 scheme
It is possible to assemble the decoder to assemble the same scheme, and it is used to switch the inputs to the y output (Fig. 2.12.2).
Fig. 2.12.2. Multiplexer and its scheme symbol
In cases where functionality Multiplexers are not satisfying developers by the number of information inputs, resort to their cascading in order to increase the number of inputs to the desired value. Most universal way Building the dimension of the multiplexer is to build a pyramidal structure consisting of several multiplexers. In this case, the first tier of the circuit is a column containing so many multiplexers as necessary to obtain the desired number of information inputs. All multiplexers of this column are switched to the same address code composed of the corresponding number of junior discharges of the shared address code. The older discharges of the address code are used in the second tier, the multiplexer of which provides the first operation of the first tier multiplexers to the general output. The cascade diagram of the multiplexer "16-1", built on multiplexers "4-1", is shown in Fig. 2.12.3.
Fig. 2.12.3. Cascade Multiplexer 16-1
The typical use of a multiplexer is the transfer of information from several sources separated in the space (sensors) of information on the input of one receiver.
Suppose that the ambient temperature is measured in several rooms and the results of these measurements must be entered into one recorder, such as computer. At the same time, since the temperature changes slowly, to obtain sufficient accuracy, it is not necessary to measure it constantly. It is enough to have information through some fixed time intervals.
The connection feature of various sources of information to one receiver on a given command and performs a multiplexer.
The multiplexer can be used as a universal logical element to implement any logical function from the number of arguments equal to the number of targeted multiplexer inputs. We show this on the example of a logical function specified by the truth table (Table 2.12.2).
Table2.12.2.
| № | A2. | A1 | A0. | Y. | № | A2. | A1 | A0. | Y. |
The scheme implementing this function is shown in Fig. 2.12.4.
Fig. 2.12.4. Implementation of the combination circuit with a multiplexer
Demultiplexer - This is a combination circuit that has one information input (D), N control (targeted) inputs (A0, A1, ..., An-1) and N \u003d 2 N outputs (y0, y1, ..., yn-1). The binary code entering the address inputs determines one of the n outputs to which the value of the variable from the information input D. Demultiplexer implements the function, reverse function of the multiplexer. It is designed to separate the data stream of one source of information in several output channels.
The functioning table of the demultiplexer (Table 2.12.2), which has 4 informational outputs (Y0, Y1, Y2, Y3) and N \u003d 2 targeted inputs (A0, A1), is presented below.
Table 2.12.2
| Inf | Address | Information outputs | ||||
| D. | A1 | A0. | Y0. | Y1. | Y2. | Y3. |
| D. | D. | |||||
| D. | D. | |||||
| D. | D. | |||||
| D. | D. |
Equations describing the operation of the demultiplexer:
Y0 \u003d d a1 * a0 *; Y1 \u003d d a1 * a0; Y2 \u003d a1 a0 *; Y3 \u003d A1 A0.
Demultiplexer scheme, built according to these equations and its graphic image Presented in Fig. 2.12.5.
Fig. 2.12.5. Demultiplexer scheme "1-4" and its conditional image
The demultiplexer function is easily implemented using a decoder, if its input "resolution" is used as a dehemultiplexer's information input, and the inputs 1, 2, 4 ... - as the address inputs of the demultiplexer A0, A1, A2, ... Indeed, with an active signal value At the entrance E is elected an output corresponding to the code filed to the address entrances. Therefore, the integral schemes of decoders having a resolving input are sometimes called not just decoders, but demultiplexer decoders.
The term "multiplexing" is called the data transfer process from several sources along the shared channel. As a device exercising on the transmitting side, the data information in one channel is used by a multiplexer. Similar device It is capable of carrying out a temporary separation of signals coming from several sources, and transmit them to the link (line) of communication in each other in accordance with the change of codes at its targeted inputs.
The receiving side is usually required to perform reverse operation - Demultiplexing, i.e. Distribution of data portions received by communication channel to sequential moments of time, on their receivers. This operation performs a demultiplexer. Sharing a multiplexer and demultiplexer for data transmission from 4 sources to
4th receivers on general line illustrates Fig. 2.12.6.
Fig. 2.12.6. Sharing Multiplexer and Demultiplexer for Data Transfer
Similar information.
As noted in paragraph 3.2, digital devices are divided into combination and sequence. The combinative includes such digital devices, the output signals depend only on the current value of the input signals. These devices, in contrast to sequence, do not possess memory. After the transitional processes are completed in these devices, the output values \u200b\u200bare set to their outputs, which the nature of the transient processes does not have.
Any complex digital device can be divided into a combination part that performs logical operations, and memory elements. In principle, the combination part can be performed on logical elements, but it is too difficult and expensive. It is much easier for this to use ready-made combinational devices. The main combinational devices include decoders, encoders, multiplexers (distributors), demultiplexers and admutors.
Decifrators
Decoder (decoder. ) – this is a combination device that allows you to recognize the numbers represented by the positional P-bit code. If at the input of the decoder "-dent binary code, then at its output code" 1 from Ν". In the code combination of this code, only one position is occupied by one, and all others are zero. For example, code "1 from Ν", Containing 4 code combinations will be represented as follows:
Such code is called unitary Therefore, the decoder is a converter of the position binary code to the unitary. Since the possible number of numbers encoded by N-bit binary code is equal to the number of sets of and arguments (N \u003d 2 "), then a decoder that has n inputs must have 2n outputs. Such an decoder is called full. If part of the input sets is not used, the decoder is called incomplete, and it has a number of outputs less than 2n. Thus, depending on the input binary code at the output of the decoder, only one of the output circuits is excited, by which the input number can be recognized.
Decifrators are used to decrypt the address cells of storage devices, highlighting letters and numbers on monitors, indicators and other devices. Most often, they are built-in bis, as, for example, in semiconductor storage devices, however, they are issued in the form of an average integration level.
We will illustrate the implementation of decoders on the example of a complete decoder of three-digit numbers. The truth table of the decoder is presented in Table. 3.5.
Table 3.5
|
x. 3 |
x. 2 |
x. 1 |
y. 0 |
y. 1 |
y. 2 |
y. 3 |
y. 4 |
y. 5 |
y. 6 |
y. 7 |
|
As you can see each way x. i is equal to one only on one set, so the operation of the decoder is described by eight functions - by the number of decodes of the decoder, each of which is conjunction (logical and) of three arguments:
A diagram of a three-bit complete decoder is shown in Fig. 3.12. To implement one function y. i, you need one three-hundredth conjunctor. Since the inputs of the conjunctors are present both direct values \u200b\u200bof arguments and inverse, in the decrypt scheme three inverters are required (see Fig. 3.12, but).
Fig. 3.12.
but – logic scheme; b. - Conditional designation of the decoder with the inputs of synchronization and permission
Often, decryptors are performed with controlled synchronization at which the code decryption will be made during the filing of the synchronizing pulse entered on the entrance FROM, only on condition that En Submitted permissive unit (see Fig. 3.12, b). To implement such a condition, conjunctors with four inputs are needed, the fourth entry of which is received by the resolution signal. This signal is formed by a two-voligal conjunctor when the signals match FROM and En.
The number of contacts at the standard case of simple is limited (14, 16 or 24), so decryptors produced in the form of IP have a small bit of the input code (three, less often four). For example, in a 16-pin case, only a three-digit complete decoder can be placed. If you want to create a larger bit decoder, a cascading connection of small bit decoders is used.
Example 3.1. Suppose on the basis of three-digit decoders, it is necessary to create a five-digit (Fig. 3.13).
Fig. 3.13.
Decision. The five-digit decoder must have 25 \u003d 32 outputs. We divide five discharges for younger x. 2, x. 1, x. 0 and senior x. 4, h. 3. Then younger can be submitted to the inputs of four 3-bit decoders of the second cascade and form 8 4 \u003d 32 outputs. Using permission inputs ΕΝ, You can choose one of the four cascade decoders, where a single signal should be formed. For this, the older two discharge will be submitted to the inputs of the first cascade control inputs, and its outputs will be connected to the permission inputs ΕΝ Decifrangers of the first cascade.
Let, for example, the input code is 11011 \u003d 2710. Since older discharges are "11", then the control decoder will allow the work of the 4th cascade decoder. At the same time, at the outputs of the first three decoders will be zeros, and at the output of the "3" fourth decoder, i.e. F. 27 There will be a logical unit.
Decifractions are widely used in technological management systems. Many actuators, such as an electric motor, an executive mechanism based on an electromagnet, can be controlled by only two commands: "Enable" and "Turn off". With this command, "Enable" convenient to match the logical "1", and the "Turn off" command is a logical "1". To manage such devices use unitary codes in which each category is rigidly related to specific device. The number of managed devices can be several dozen, and the decoder must have an appropriate number of outputs.
In fig. 3.14 shows the scheme of eight executive devices based on the decoder. The scheme contains eight similar chains that enable / disable the actuator. The status of the actuator is fixed by an element of memory, which is most often used by a trigger (see paragraph 3.9). The top input provides the inclusion of the item, and the bottom is shutdown. The signal that determines the on-or-off state is enabled to the corresponding circuits and (upper or lower) of all memory elements, but this signal is perceived only by the element that is selected by the decoder. To do this, on the control scheme, along with ON / OFF signals, a code arrives at the same time entering the decoder and the defining number of the actuator. The signal from the output of the memory element is enhanced and enters the inclusion circuit of the actuator. Here it is possible to install a optoconan galvanic junction (see paragraph 2.10), an electromagnetic relay that provides a high comprising voltage supply, for example \u003d 220 V, an electromagnetic starter that feeds the three-phase voltage to the electric motor.
Fig. 3.14.
Encipher
Encifrator (Coder) – this is a combination device that performs functions, inverse decryptor. When the signal is submitted to one of its inputs (unitary code), the appropriate binary code should be formed at the output.
If the number of encoder inputs is 2n, then the number of outputs obviously should be equal p, those. The number of discharges of the binary code that can be encoded 2 "situations.
Illustrate the synthesis of the encoder scheme when p \u003d 3. Tatac of truth is viewed in Table. 3.6.
Table 3.6.
|
h. |
h. |
||||||
|
y. 3 |
y. 2 |
y. 1 |
y. 3 |
y. 2 |
y. 1 |
||
The work of the encoder is described by three functions. w. 3, U. 2, y. 1, each of which is equal to one on four sets (the dial number corresponds to the input number). SCOPNF Output functions are equal:
Three functions are implemented by three disjunctors (Fig. 3.15), on the outputs of which a three-bit binary code is formed.
Fig. 3.15.
At the same time, the argument x. 0 Not included in any of the logical functions and tire x. 0 remains unused. Indeed, the X0 input signal must correspond to the "000" code, which will still be at the output of the encoder if all other arguments are zero.
In addition to ordinary encoders, there are also priority encoders. Such encoders perform a more complex operation. When operating a computer and other devices, the task of determining the priority service provider is often solved. Several competitors put their service requests that cannot be satisfied at the same time. You need to choose who is provided with the right of priority service. The simplest option Tasks - assigning a fixed priority requests to each source. For example, a group of eight requests R. 7, ..., R. 0 (R. - From the English. request - Request) The unit is formed that the highest priority has a source of number seven, and then the priority decreases from the number to the number. The youngest priority of the bullet source - it will be served only in the absence of all other requests. If there are several requests simultaneously, a request with the largest number is served.
The priority encoder produces a binary number of senior request at the output. If you have only one excited login, the priority encoder works in the same way as binary. Therefore, in the series, the binary encoder as an independent element may be absent. His work mode - private case Work priority encoder.
The decoder (decoder) is a combination device with several inputs and outputs that certain combinations of input signals correspond to the active state of one of the outputs. Decifranisoms convert binary or binary-decimal code to the unitary code. If the decoder has n. entrances, m. outputs and uses all possible sets of input variables, then m. = 2 n. . Such a decoder is called complete. If only part of the sets is used, this decoder is called incomplete. Decifractions use when you need to access various digital devices, and the device number (its address) is represented by binary code. The inputs of the decoder (targeted inputs) are often numbered by non-sequence numbers, but according to the weights of binary discharges, i.e. not 1, 2, 3, 4, and 1, 2, 4, 8.
Formally, describe the work of the decoder, by setting a list of functions worked out by each of its outputs. Y. i. . So, for decoder 3-8:
Y. O \u003d; Y. 1
=
;Y. 2
=
;
Y. 3
=
;
... Y. 7
=a. 4 a. 2 a. 1 .
The number of inputs and outputs of the decoder indicate as follows: decoder 3-8 (read "three to eight"); 4-16; 4-10 (this is an incomplete decoder). The implementation of the above-mentioned eight expressions with the help of eight three-hundredth elements and (Fig. 10.7) gives the simplest decoder, called linear.
but b.
Fig. 10.7. Decifranger 3-8: but - symbol; b. - Structure
The main volume of its equipment in the general case m. n.- Business elements I. In addition, equipment is usually attributed n. inverters input variables and n. buffer input amplifiers that reduce the unit of load of the signal source.
Decifrators often have a permitting entrance EI. For EI \u003d 1 Decifranist works as usual, and when EI \u003d 0 At all outputs, not active levels are installed.
entrance EI It affects all elements I. In the scheme (Fig. 10.8), the impact turns out to be through the direct and inverse inputs of one of the input code discharges (through additional elements and). At the same time, the number of elements inputs does not change, but additional delay is made to the operation of the decoder. In the diagram (Fig. 10.9), the delay is not made, but here the elements have a greater number of inputs.
Resolving input EI often performed inverse. An decoder having a resolving input is sometimes called a demultiplexer decoder and instead of notation DC Use the designation DX. This is due to the fact that the entrance EI Sometimes used as an informational (as in demultiplexers).
Fig. 10.8. Resolution through direct and fig. 10.9. Resolution through
inverse entrances of one of the discharges Additional inputs of elements and
entrance EI Used in constructing tree (cascading) decoder schemes in order to expand the address space. In this case, all the address space is divided into groups. Senior addresses are fed to the senior discharge decodes, whose outputs are inputs EI Manage the second cascade decoders. In fig. 10.10 The diagram of a two-stage decoder 5-32 (five thirty-two) is presented.
Fig. 10.10. Two-stage decoder 5-32.
Two senior discharge addresses but 16 I. but 8 decoded by decoder 2-4 DC4, which is inputs E.I. Controls the four cascade decoders. Junior addresses but 4 , but 2 , but 1 go to all the decoders of the second cascade, but open at the entrance EI it turns out only one of them. He will belong to him the only one of all 32 excited exit. For example, the input code 01111 has an decoder DC4 makes an active output 1. This signal will open the second stage decoder DC1, A. DC0, DC2, DC3 closed. At the decoder DC1 The signal will appear on the output 7, which corresponds to 15 output of the entire decoder. This principle is used when constructing a decoder on many outputs from microcircuits of decoders with a smaller number of outputs.
In the case examined, the 5-bit address was divided into two groups in 2 and 3 discharge. This determined the structure of the decoder. In general, the multi-digit address can be divided into groups in various ways and each will correspond to its own version of the circuit. Options will vary with delay and hardware costs. Thus, it is possible to set the task of choosing the optimal, in a given series of elements, structure.
In fig. 10.11 The two-stage decoder 4-16 is shown, the second cascade of which is assembled according to the scheme of the rectangular decoder. The drops of addresses are divided into two groups, each of which is independently decrypted by its first cascade decoder DC0 I. DC1. At any combination of the input variables, one line and one grid column are selected, in the nodes of which are elements and second steps (second cascade). As a result, each input kit excites the yield of a single element corresponding to it. Such a mesh from the elements is called a rectangular or matrix decoder.
Fig. 10.11. Matrix decoder
Divide the drops of the address between DC1 I. DC2 It is necessary if possible equally. The closer the rectangle of the second cascade to the square, with the same number of the output elements and, less than the sum of its rows and columns, i.e., less than the number of exits of the first cascade decoders. It follows from this that the use of a square matrix in the second cascade allows to apply the most simple decoders in the first cascade and thereby minimizing the overall delay in the work of the entire decoder.
As an entry EI (E.) The entire two-stage decoder is convenient to use the allowing entry of only one of the first cascade decoders. At the same time, or all rows or all columns are locked.
It should be noted that with a large number of exits (hundreds or more), the rectangular decoder is the most economical equipment, which explains its use in the bis of memory. With a small number of outputs, a linear decoder is the most economical.
Decifrators manufactured in the form of chips have an alphabetic ID, for example, 155ID3, 155ID4. In series TTL, the decoders usually have inverse outputs, i.e., a low level is active. In the CMOS series, the output signals more often have an active high level.
Often, several resolution inputs are made in the chips of decoders, and the solving combination is their conjunction. At the same time, it is convenient to build decoders, using a cascade principle and building the first cascade of decryption not on a separate special decoder, but collecting it from the conjunctors of the resolution inputs. In fig. 10.12 The decoder 5-32 of 4 decoders 3-8 is represented. Each microcircuit has two inverse resolution entrances. Symbol & Above Symbol E.I. Indicates that the resolution exists only when all signals of a group of inputs are labeled &. In the figure, the symbols of inversion indicate the coincidence of two low levels At the entrances permission.
The first cascade decoder is distributed according to the conjunctors of 4 microcircuits. This solution is to have several permissive inputs related to the operation and to collect fragments of decoders on these inputs, in general typical of modern chips.
Fig. 10.12. Decifractions of addresses using permitting inputs in the first stage
If you use only two decoders DC0 I. DC1, then you can get an decoder on 16 outputs. In this case, the address entry but 16 will be absent, and the lower (according to the scheme) authorizing inputs of decoders DC0 I. DC1 must be grounded.
The diagram of the decoder 155id4 is presented in Fig. 10.13. It includes two decoders 2-4. Each decoder has a couple of resolution inputs. One permissive input of one of the sections is inverted. This allows you to combine it with a non-inverted authorizing input of another section and submitting the third variable for this pair. but 4, use the same scheme as a decoder 3-8 with a resolution E.. In addition, this chip can be used as two demultiplexers with 1 inputs of 4 outputs and as a demultiplexer from one line to 8 outputs.
Fig. 10.13. Scheme of decoder 155id4.
Fig. 10.14. Connection options 155In decoder
In fig. 10.14 shows the possibility of using a microcircuit 155id1 in the qualities of the decoder 4-10 or 3-8. In the submitted scheme, when using all four inputs, an alifrator of 4-10 is an addressed microcircuit. If the input 8 is used as a resolution input, then the microcircuit will be an decoder 3-8. Outputs 8 and 9 are not used.
Decifractions can be used as a demultiplexer of input signals, and together with the encoder are used when constructing codes converters, selection of specified input codes, etc.. To implement such devices, programmable logical matrices or programmable logical integrated circuits (PLM or PLIS) can be used.
3.1.2 Encipher
Encryption is a way to compress data by conversion m.-drawing unitary (decimal) code in n.-drawn binary or binary-decimal code ( m.> n.). Enciprators ( CD, coder.) Perform a function, reverse function of the decoder. When the signal is received, the code corresponding to the number of this entry is generated to one of the inputs of the encoder at its outputs.
Full encoder ( m. – n.) It has m. = 2 N. Entrances I. n. Outputs, if m. < 2 N., then the encoder is not complete. It can also be non-executive if only one active signal is allowed or prioritized if several active signals on the inputs are allowed simultaneously.
The principle of operation of a complete non-executive encoder (4 - 2) is illustrated by the truth table (Table 1).
The truth table of the non-executive encoder (4 - 2) Table 1
|
Set |
Information entrances |
Outputs |
||||
|
X. 3 |
X. 2 |
X. 1 |
X. 0 |
F. 1 |
F. 0 |
|
Maps of carno to minimize the encoders scheme are usually not used due to the complexity of compilation with a large number of variables.
From the table (1) it follows that the younger dischargeF. 0 the code at the output of the encoder is equal to one when a unit is present on odd inputs:
Senior dischargeF.
1
code at the release of the encoder is equal to one when at the entrancesX.
3
,
X.
2
there is a unit:
Consequently, the circuit of the encoder (4 - 2) can be implemented using two elements 2 liters (Fig. 1, a).
Fig. 1 non-executive encoder schemes (4 - 2) on elements 2Ili (a), 2I-not (b)
For inverse recording (Fig. 1, b):
One of the input signals of the encoder necessarily has a single value (Table 1). If at the entrances X. 1 , X. 2 , X. 3 zero values means chthen at the entrance X. 0 logicalthe unit corresponding to the set 0 and this input to the diagram may not be connected (Fig. 1, a). Similar toX. 3 in the schemeencifrator in fig. 1, b. The schemes of encoders in the figure are distinguished by the mirror permutation of the inputs (in both cases younger discharge X. 0 , olderX. 3 ) and inverting output signals (Fig. 1, b).
Enciprators usually have service entrances and outputs:
- permissive (gating) entranceEI (En ) To select the triggering time of the encoder, providedEI \u003d 1, also for increasing the discharge of the input code.
- Allive outputEO (En ), defines the lack of signals at all information outputs (EO \u003d 1). Used to increase bit by connecting additional encoders, connection condition EO =1.
- Allive outputGS. (CS. ), indicates the presence of an information signal at least in one entrance, taking the valueGS. \u003d 1. Provides coordination of the work of the encoder and external devices (microprocessor). It can be used in the encoder bit increment scheme to exclude code conversion errors.
One of the main appointments of the encoder is to enter data into digital devices using the keyboard. Encodes that, while simultaneously pressing multiple keys, produce code only the highest digit, are called priority. If these encoders detect the older (left) unit and form a binary code of the corresponding unit of the decimal number, then called pointers senior unit (Element designation Hpr. 1/ Bin. ).
In the truth table of the senior unit (Table 2), the X symbol indicates the values \u200b\u200bof input variables that are not important to the device and can be equal to 0 or 1. Interest represent units in the older discharge of the corresponding set.
The "-" symbol indicates the values \u200b\u200bof the variables that are not entered into the encoder, because On the resolution entranceEI logical zero signalat the exitF. 1 F. 0 = 00.
Example: If the older discharge key is pressed H. 3 (Set 5), which corresponds to codes 3 10 \u003d 11 2, pressing other keys should be ignored.
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Tatac of the truth of the senior pointer (4 - 2) Table 2 |
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|
Set |
Service |
Information |
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|
entrance |
outputs |
Inputs |
Outputs |
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|
EI |
GS. |
EO |
X. 3 |
X. 2 |
X. 1 |
X. 0 |
F. 1 |
F. 0 |
|
In accordance with the gluing rule for the exit F. 1 .
Laboratory work is performed using the Leso2 training laboratory stand.
1 goal of work
The purpose of the work is to study the principles of the action of combinational schemes: decoder, encoder, code converter for sevegmental indicator, multiplexer, adder.
2 short theoretical information
2.1 Decifranger (decoder)
The decoder (decoder) is used to convert the N-bit positional binary code into a single output signal on one of 2N outputs. At each input combination of signals on one of the outputs, it appears 1. Thus, on a single signal on one of the outputs, you can judge the input code combination. The truth table for a decoder with two inputs is shown in Table 2.1.
Table 2.1 - Table of truth two-digit decoder
| x1. | x2 | y0. | y1. | y2. | y3. |
| 0 | 0 | 1 | 0 | 0 | 0 |
| 0 | 1 | 0 | 1 | 0 | 0 |
| 1 | 0 | 0 | 0 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 1 |
To build a decoder scheme on the truth table, we use the method described in the laboratory work No. 1 performed on the LESO2 booth. For example, the device must have 4 outputs. For each output, write a logical expression. On the basis of the SDNF:
y0 \u003d x1 · x2
y1 \u003d x1 · x2
y2 \u003d x1 · x2
According to this system of expressions, it is easy to build a diagram of the desired decoder (Figure 2.1).
Figure 2.1 - Decifranitor scheme The conditional graphic designation of such an decoder is shown in Figure 2.2.
Figure 2.2 - Conditional graphic designation of the decoder 2.2 Encoder (encoder)
The encoder performs a function, reverse decoder (decoder), that is, it converts the non-procurable (unitary) binary 2N discharge code into n discharge position code. When the unit signal is applied to one of the inputs, the appropriate binary code is formed at the output. Make a table of truth of the encoder at n \u003d 2.
Table 2.2 - the truth table of the encoder at n \u003d 2
| x1. | x2 | x3. | x4. | y1. | y0. |
| 1 | 0 | 0 | 0 | 0 | 0 |
| 0 | 1 | 0 | 0 | 0 | 1 |
| 0 | 0 | 1 | 0 | 1 | 0 |
| 0 | 0 | 0 | 1 | 1 | 1 |
Synthesize the encoder. To do this, write down the system of its own functions:
y1 \u003d x1 · x2 · x3 · x4 + x1 · x2 · x3 · x4
y0 \u003d x1 · x2 · x3 · x4 + x1 · x2 · x3 · x4
Figure 2.3 - Enciprator Scheme 
Figure 2.4 - Conditional graphic designation of the encoder 2.3 Code Converter for Sevegment Indicator
The most wide codes converters are known for digital indicators. For example, the converter of the 4-bit positional binary code into decimal numbers. There is a seven segment indicator and it is necessary to highlight ten digits.
Figure 2.5 - Seven Segment Indicator It is obvious that the binary code should have at least 4 digits (2 ^ 4 \u003d 16, which is more than 10). We will make a table of truth of such a converter.
Table 2.3 - Converter Trial Table
| Numeral | Binary code 8-4-2-1 | a. | b. | in | g. | d. | e. | j. | |||
| 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |
| 1 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 |
| 2 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 1 |
| 3 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
| 4 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 |
| 5 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 1 | 1 |
| 6 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 1 |
| 7 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 |
| 8 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
| 9 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 |
It is easy to make a system of eigenfunctions for all outputs, i.e. SDNF minimize it and make a fundamental scheme.
Figure 2.6 - Conditional graphic designation of the code converter 2.4 Multiplexer
A multiplexer is a device that allows you to switch one of 2 ^ n of information inputs x by one y output under the action of N control (address) signals. On the image. 2.7 shows a simplified multiplexer functional diagram on idealized electronic keys.
Figure 2.7 - Multiplexer diagram on idealized electronic keys In digital circuits you need to manage keys using logical levels. Therefore, it is desirable to choose a device that could perform functions electronic key With a digital signal control. Let's try to "make" the logical elements already familiar to us as an electronic key. Consider the typical element "and". At the same time, one of the inputs of the logical element "and" will be considered as an electronic key information input, and the other input is as a controller. Since both inputs of the logical element "and" are equivalent, it does not matter which of them will be the management entrance. Let the input of X be the manager, and Y - information. For simplicity of reasoning, we divide the Ti into two parts depending on the level of the logical signal on the control input X.
Table 2.4 - Total Tank
| y. | x. | Out. |
| 0 0 |
0 1 |
0 0 |
| 1 1 |
0 1 |
0 1 |
According to the truth table, it is clear that if the zero logical level is filed to the control input X, the signal filed to the Y input, does not pass to the output. When a logical unit is applied to the control input, the signal entering the Y input appears at the output OUT. This means that the logical element "and" can be used as an electronic key. It does not matter which of the element inputs "and" will be used as a control entrance, and which is as an information. It remains only to combine the outputs of the elements "and" to one common output. This is done using the logical element "or" in the same way as when constructing a scheme according to an arbitrary truth table. The resulting version of the switch circuit with the logical level control is shown in Figure 2.8.
Figure 2.8 - Schematic scheme Multiplexer made on logical elements In the circuits shown in Figures 2.7 and 2.8, you can simultaneously include several inputs per exit. However, it usually leads to unpredictable consequences. In addition, a lot of inputs are required to manage such a switch, therefore, the multiplexer usually includes a binary decoder, as shown in Figure 2.9. Such a scheme allows you to control the switching of the multiplexer information inputs using binary codes supplied to its control inputs. The number of information inputs in such schemas is chosen in a multiple degree of numbers two.
Figure 2.9 - Schematic diagram of a multiplexer controlled by binary code The conditional graphic designation of the 4-in-in multiplexer with the binary code control is shown in Figure 2.10. The inputs A0 and A1 are control of the multiplexer inputs that define the address of the information input signal, which will be connected to the output output of the multiplexer Y. Information input signals are indicated: x0, x1, x2 and x3.
Figure 2.10 - Conditional graphic designation of 4 entry multiplexer In the conditional graphic designation of the name of information inputs A, B, C and D is replaced by the names X0, X1, X2 and X3, and the OUT output name is replaced by the name Y. This designation of the inputs and the outputs of the multiplexer is more common in domestic literature. Address inputs are indicated as A0 and A1.
On the features of the implementation of multi-flags in the Verilog language, you can read in the article:
Flag architecture. Part 2. Multiplexer
2.5 Adder
The adder is a computer node designed for the addition of binary numbers. The construction of binary adders usually begins with the adder module 2.
Adder module 2
The diagram of the adder in module 2 coincides with the scheme excluding "or".
Table 2.5 - Tatt of the truth of the adder module 2
| x1. | x2 | y. |
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
A logical expression describing the adder for module 2:
y \u003d x1 · x2 + x1 · x2
Figure 2.11 - Conditional graphic designation of the adder module 2 Based on a logical equation describing this element, you can synthesize the scheme:
Figure 2.12 - Chart of adder for module 2 The adder for module 2 performs summation without carrying out the transfer. In the usual binary adder you need to take into account the transfer, therefore schemes are required to form transfer to the next binary discharge. The truth table of such a scheme called the semi-channel is given in Table 2.6.
Table 2.6 - half the truth table
| A. | B. | S. | P0. |
| 0 | 0 | 0 | 0 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 1 |
Here A. and B. - terms;
S. - amount;
P0. - transfer to the senior discharge (Pout transfer output).
Write the system of own functions for the half-chamber:
S \u003d a · b + a · b
P0 \u003d A · B
Figure 2.13 - Schematic diagram implementing a half-chamber truth table 
Figure 2.14 - image of a half-chamber in diagrams Full adefficient.
The diagram of the semicumor forms the transfer to the senior discharge, but cannot take into account the transfer from the younger discharge. When adding multi-digit binary numbers, three digits should be folded in each discharge - 2 terms and transfer unit from the previous discharge PI.
| PI | A. | B. | S. | PO |
| 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 1 | 0 |
| 0 | 1 | 0 | 1 | 0 |
| 0 | 1 | 1 | 0 | 1 |
| 1 | 0 | 0 | 1 | 0 |
| 1 | 0 | 1 | 0 | 1 |
| 1 | 1 | 0 | 0 | 1 |
| 1 | 1 | 1 | 1 | 1 |
PI - input 1 transfer from the previous discharge,
PO - Exit 1 transfer to the senior discharge.
Based on the truth table, we write a system of eigenfunctions for each output:
S \u003d a · b · pi + a · b · pi + a · b · pi + a · b · pi
Po \u003d A · b · pi + a · b · pi + a · b · pi + a · b · pi
As a result, we obtain a comprehensive chart (Figure 2.15).
Figure 2.15 - Schematic diagram that implements the truth table of a complete binary single-digit adder 
Figure 2.16 - Image of a complete binary single-digit adder in the diagrams
| Theory Questions |
3 job task
3.1 Explore the principle of operation of the decoder 2 x 4
Configure FPGA in accordance with Figure 3.1. Connect to inputs X0 and X1 switches S7 and S8, and to y0, y1, y2, y3 outputs LED indicators LED5, LED6, LED7, LED8. To do this, connect the inputs and outputs of the decoder to the appropriate felling legs.
Figure 3.1 - Decifranitor scheme Feeding all possible combinations of logical levels to the inputs X0, X1 using the S7, S8 keys and watching the states lED indicators LED5, LED6, LED7, LED8, fill in the truth table of the decoder.
Table 3.1 - Decifranger Table
| x1. | x2 | y0. | y1. | y2. | y3. |
| 0 | 0 | ||||
| 0 | 1 | ||||
| 1 | 0 | ||||
| 1 | 1 |
3.2
Explore the principle of operation of the encoder 4x2
Configure FPGA in accordance with Figure 3.2.
Figure 3.2 - 4x2 encoder scheme Connect to the inputs x1, x2, x3, x4 switches S8, S7, S6, S5, and to y0, y1 outputs LED8, LED7. To do this, connect the inputs and outputs of the decoder to the appropriate felling legs. Feeding all possible combinations of logical levels to the inputs x1, x2, x3, x4 using keys S8, S7, S6, S5 and watching the states of LED7 LEDs, LED8, fill in the truth table of the encoder.
Table 3.2 - the truth table of the encoder
| x1. | x2 | x3. | x4. | y1. | y0. |
| 1 | 0 | 0 | 0 | ||
| 0 | 1 | 0 | 0 | ||
| 0 | 0 | 1 | 0 | ||
| 0 | 0 | 0 | 1 |
3.3 Explore the operation of the code converter for the seven indicator.
Create a table of the truth of the code converter (Table 3.3).
Collect the scheme shown in Figure 3.3.
Table 3.3 - Converter Trial Table
| x3. | x2 | x1. | x0. | A. | B. | C. | D. | E. | F. | G. |
| 0 | 0 | 0 | 0 | |||||||
| 0 | 0 | 0 | 1 | |||||||
| 0 | 0 | 1 | 0 | |||||||
| 0 | 0 | 1 | 1 | |||||||
| 0 | 1 | 0 | 0 | |||||||
| 0 | 1 | 0 | 1 | |||||||
| 0 | 1 | 1 | 0 | |||||||
| 0 | 1 | 1 | 1 | |||||||
| 1 | 0 | 0 | 0 | |||||||
| 1 | 0 | 0 | 1 |
Figure 3.3 - Code Converter Scheme for Sevegment Indicator Feeding using keys S8, S7, S6, S5 various code combinations on the inputs x0, x1, x2, x3, determine the numbers displayed on the indicator. According to the experiment, fill in Table 3.4.
Table 3.4 - Table that describes the operation of the code converter for the seven indicator
| x3. | x2 | x1. | x0. | Indicator reading |
| 0 | 0 | 0 | 0 | |
| 0 | 0 | 0 | 1 | |
| 0 | 0 | 1 | 0 | |
| 0 | 0 | 1 | 1 | |
| 0 | 1 | 0 | 0 | |
| 0 | 1 | 0 | 1 | |
| 0 | 1 | 1 | 0 | |
| 0 | 1 | 1 | 1 | |
| 1 | 0 | 0 | 0 | |
| 1 | 0 | 0 | 1 |
3.4 Explore Multiplexer 4x1
Configure FPGA in accordance with Figure 3.4.
Figure 3.4 - Multiplexer diagram 4x1 Alternately establishing all possible code combinations on targeted inputs A and B, determine the numbers of the switched channels. The commutable channel number is determined by one-time connection to the inputs x0, x2, x3, x4 of the logical unit level and observation of y output. Fill in Table 3.5.
Table 3.5 - Table describing the operation of the multiplexer
3.5 Explore the chart of adder
Configure PLITS in accordance with Figure 3.5. Here PIN., Pout. Accordingly, the input and output unit of transfer, A. and B. - terms, S. - Amount.
Figure 3.5 - Chart of adder Fill out the truth table of the adder (Table 3.6).
Table 2.7 - Tatt of true adder truth
| PIN. | B. | A. | Pout. |
| 0 | 0 | 0 | |
| 0 | 0 | 1 | |
| 0 | 1 | 0 | |
| 0 | 1 | 1 | |
| 1 | 0 | 0 | |
| 1 | 0 | 1 | |
| 1 | 1 | 0 | |
| 1 | 1 | 1 |
- Purpose of work.
- Study schemes of the decoder, encoder, code converter for the seven indicator, multiplexer, adder.
- Total Tables for each scheme.
- Conclusions for each task.
5 Control questions
- The principle of the work of the decoder?
- How to synthesize an arbitrary discharge decoder?
- How does the encoder work?
- How does the code converter work for the seven indicator?
- How is the seven segment indicator arranged?
- How does a multiplexer work?
- How in laboratory work A multiplexer study was conducted?
- How does the adder work?
- Picture the truth table of the encoder.
- What is a transfer unit?